`timescale  1ns / 1ps
module testbench_demo;

parameter PERIOD  = 10;

reg aclk = 0;

reg s_axis_a_tvalid;
wire s_axis_a_tready;
reg [31 : 0] s_axis_a_tdata;

reg s_axis_b_tvalid;
wire s_axis_b_tready;
reg [31 : 0] s_axis_b_tdata;

wire m_axis_result_tvalid;
reg m_axis_result_tready;
wire [31 : 0] m_axis_result_tdata;

// 时钟信号
initial
begin
    forever #(PERIOD/2)  aclk=~aclk;
end

initial
begin
	#100
	s_axis_a_tvalid <= 1'b1;
	s_axis_a_tdata <= 32'b01000000011111110010101100000010;
	s_axis_b_tvalid <= 1'b1;
	s_axis_b_tdata <= 32'b01000000100001100111111011111010;
end

top u_top(
.aclk					(aclk					),
.s_axis_a_tvalid		(s_axis_a_tvalid		),
.s_axis_a_tready		(s_axis_a_tready		),
.s_axis_a_tdata			(s_axis_a_tdata			),
.s_axis_b_tvalid		(s_axis_b_tvalid		),
.s_axis_b_tready		(s_axis_b_tready		),
.s_axis_b_tdata			(s_axis_b_tdata			),
.m_axis_result_tvalid	(m_axis_result_tvalid	),
.m_axis_result_tready	(m_axis_result_tready	),
.m_axis_result_tdata	(m_axis_result_tdata	)
);

endmodule